I. Field of the Invention
The present invention relates generally to bipolar transistors and, more particularly, to an integrated circuit having various types of bipolar analog and digital, NPN and PNP transistors and the process for fabricating same.
II. Description of the Related Art
Since the middle 1970's the semiconductor industry has endeavored to develop integrated circuits that would handle the higher current and voltage requirements necessary to interface man and his machines. Interfacing continues to be a difficult problem due to the inherent limitations on power handling of device structures fabricated by conventional integrated circuit processes. For example, early bipolar processes were developed using either PNP or NPN vertical power transistors. These processes were primarily compromises that either built power components using standard logic processes resulting in very poor power handling capability and limited safe operating area performance, or when power processes have been used, the long diffusion temperature cycles and heavy dopant concentrations required have yielded only the most crude and basic logic functions with very low density capabilities.
Modern trends to solve the above problems have been to combine Diffused Channel MOS (DMOS) transistors as a power device with bipolar devices and later with high density CMOS logic. One of the primary successes of this DMOS/CMOS-bipolar technology is that higher logic densities have been possible, opening the door to integrated circuits that could handle medium power with high logic density. The major drawback to this technology becoming widely used is that DMOS technology has proved to be less rugged than bipolar components. Another problem is that there appears to be a division of the voltage levels at which each technology performs best DMOS solutions excel below 60 volts, bipolar solutions excel above 200 volts. The best choice for the middle ranges depends on the specific applications.
Therefore it should be apparent that a need exists for a semiconductor process that enables the combination of high power bipolar transistors with either bipolar or CMOS logic and analog circuitry without the voltage, current and ruggedness compromises typically associated with merged technologies.